Espressif Systems /ESP32-P4 /SPI0 /SPI_SMEM_AXI_ADDR_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SPI_SMEM_AXI_ADDR_CTRL

Description

SPI0 AXI address control register

Fields

SPI_MEM_ALL_FIFO_EMPTY	The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.
SPI_RDATA_AFIFO_REMPTY	1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
SPI_RADDR_AFIFO_REMPTY	1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
SPI_WDATA_AFIFO_REMPTY	1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
SPI_WBLEN_AFIFO_REMPTY	1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
SPI_ALL_AXI_TRANS_AFIFO_EMPTY	This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.

Links

() ()